Flash memory is a commonly used type of non-volatile memory in widespread use as storage for consumer electronics and mass storage applications. Flash memory is pervasive in popular consumer products such as digital audio/video players, cell phones and digital cameras, for storing application data and/or media data. Flash memory can further be used as a dedicated storage device, such as a portable flash drive pluggable into a universal serial port (USB) of a personal computer, and a magnetic hard disk drive (HDD) replacement for example. It is well known that flash memory is non-volatile, meaning that it retains stored data in the absence of power, which provides a power savings advantage for the above mentioned consumer products. Flash memory is suited for such applications due to its relatively high density for a given area of its memory array.
FIG. 1 is a block diagram of an asynchronous flash memory device of the prior art. Flash memory device 10 includes interface and control circuits also known as peripheral circuits, and core circuits. The interface and control circuits includes I/O buffers 12, 14 and 16, registers 18, 20, 22, and control circuit 24. The core circuits include a high voltage generator 26, a row predecoder 28, a row decoder 30, a column predecoder 32, a column decoder 34, a page buffer 36, and a memory array 38. Those of skill in the art should understand the function of the circuits of the interface and control circuits, and many details are not shown in order to simplify the schematic. For example, the lines interconnecting the circuit blocks merely illustrates a functional relationship between connected blocks, without detailing the specific signals being used. The output buffer 12 drives the R/B# output pin or port, the control buffers 14 include input buffers each connected to a respective input control pin or port, and the data buffers 16 include bi-directional buffers for receiving and driving data onto a respective I/O pin or port. In the presently described example, the control buffers 14 includes input buffers for the CE#, CLE, ALE, WE#, RE# and WP# input control pins or ports. There are eight data I/O pins or port in the presently described example, therefore there are eight bi-directional buffers. Asynchronous input buffers and output buffer circuits are well known in the art, and do not need to be described in any further detail.
To execute operations such as erase, program and read in asynchronous flash memory device 10, a command is provided via the data I/O pins. This command can include an operational code (OP code) that corresponds to a specific operation, address information and data, depending on the operation being executed. It is noted that because address and write (program) data can be more than 8 bits in length, several input iterations or cycles may be required before all the address and write data bits are latched in the proper registers. The OP code data is latched in the command register 18, and address information for read and program operations is latched in address register 20. The OP code data is provided to the control circuit 24, which includes logic for decoding the OP code, such as a command decoder or interpreter for example. The control circuit 24 includes control logic that generates the internal control signals with the required timing for operating both the core circuits and any peripheral circuits of the flash memory device 10.
The core circuitry consisting of a high voltage generator 26, row predecoder 28, row decoder 30, column predecoder 32, column decoder 34, page buffer 36, and memory array 38 are well known to persons familiar with flash memory. The high voltage generator 26 is used for read, program and erase operations. In terms of a read operation, a circuit description relating to this is provided below.
With respect to a read operation, the row predecoder 28 receives a row address from address register 20 while the column predecoder 32 receives a column address from address register 20. The predecoded row signals are used by the row decoder 30 to drive a wordline of memory array 38 for accessing a page of data. The data stored in the memory cells connected to the selected wordline are sensed and stored in the page buffer 36 via bitlines. In the example memory array 38, continuous wordlines extend horizontally from the left side at the row decoder 30 to the right side of the memory array 38. The predecoded column signals are used by column decoder 34 for selecting a set of 8 bits of data from the page buffer 36 to output to the data buffers 16. 8 bits are used by example, but other configurations can be used. It should be noted that the sequence and timing of asserted control signals originates from the control circuit 24 in response to the received OP code.
FIG. 2 is a schematic showing the basic organization of any NAND flash memory array. Memory array 40 is organized as blocks Block[1] to Block[k], and each block consists of pages WL1 to WLi where. Both k and i are non-zero integer values. Each page corresponds to a row of memory cells coupled to a common wordline. A detailed description of the memory cells of the block follows. Each block consists of NAND memory cell strings, having flash memory cells 42 serially coupled to each other. Accordingly, wordlines WL1 to WLi are coupled to the gates of each flash memory cell in the memory cell string. A string select device 44 coupled to string select line signal SSL selectively connects the memory cell string to a bitline 46, while a ground select device 48 coupled to ground select line signal GSL selectively connects the memory cell string to a source line, such as VSS. The string select device 44 and the ground select device 48 are n-channel transistors in the presently described example. Bitlines BL1 to BLi 46, where j is a non-zero integer value are common to all blocks of memory array 40, and each bitline 46 is coupled to one NAND memory cell string in each of blocks [1] to [k]. Each wordline WL1 to WLi, SSL and GSL signal is coupled to the same corresponding transistor device in each NAND memory cell string in the block. As those skilled in the art should be aware, data stored in the flash memory cells along one wordline is referred to as a page of data.
Coupled to each bitline outside of the memory array 40 is a page buffer 50 for storing one page of write data to be programmed into one page of flash memory cells. The page buffer 50 also includes registers, sense circuits for sensing data read from one page of flash memory cells, and verify logic. During programming operations, the page buffer 50 performs program verify operations to ensure that the data has been properly programmed into the flash memory cells coupled to the selected wordline. To achieve high density, each flash memory cell can either be single level cells (SLC) for storing two logic states, or multi-level cells (MLC) for storing at least two bits of data.
Returning to FIG. 1, the memory array 38 with its corresponding row decoder 30, page buffer 36 and column decoder 34 are commonly referred to as a plane. The size of this plane will reach a practical limit, which is defined by the length of the wordlines and the bitlines. This can be due to a reduction in performance, yield or a combination thereof when the wordlines and bitlines become too long, which is an effect that is well known to persons of skill in the art. One known technique for addressing this problem is to place the row decoder in the middle of the memory array, thereby resulting in segmented physical wordlines that are logically the same. This allows the plane to be increased in size because the row decoder can be shared. One of the driving factors for increasing the size of the plane is the desired increase in the page size. Large page sizes are well suited for multi-media applications such as music, photo and video because the file size to be programmed is typically larger than the maximum page size. Furthermore, the total program time may be nearly the same regardless of the page size, thereby resulting in higher program throughput that further benefits multi-media applications.
While the length of the wordline segments in a plane can be increased, eventually the same performance and yield problems will arise as the wordline lengths are increased. Therefore to accommodate large capacity memory devices, a second plane is introduced as part of the memory array. FIG. 3 is an illustration of a memory array, such as memory array 38 of FIG. 1, organized as two planes.
In FIG. 3 plane 60 includes two sub-arrays 64 and 66 positioned on both sides of a row decoder 60, and a page buffer 68 located at one end of sub-arrays 64 and 66. Plane 62 includes two sub-arrays 70 and 72 positioned on both sides of a row decoder 74, and a page buffer 76 located at one end of sub-arrays 70 and 72. Collectively, page buffers 68 and 76 store one page of data. Each sub-array has the basic NAND flash memory organization shown earlier in FIG. 2. In this example, both sub-arrays of each plane shares one common row decoder, such that the same logical wordline extends horizontally from the row decoders into each sub-array. It is assumed that the page buffers include the column decoding circuits shown in FIG. 1.
In the two plane memory array configuration of FIG. 3, one page of data is read or programmed by simultaneously selecting, or activating, one row in both planes 60 and 62. For example, plane 60 is programmed by loading page buffer 68 with a half page of data and page buffer 76 with the other half page of data, then executing programming operations to write the data to page portions 78 and 80. When reading for example, one row in both planes 60 and 62 (ie. pages 78 and 80) is activated and the data is sensed and stored in page buffers 68 and 76 for subsequent burst read-out.
While multi-media applications reap the benefits of increasing page sizes, other applications using such NAND flash memory will suffer from degraded performance and reliability. Such applications include flash cache and solid state drives (SSD) for hard disk drive (HDD) replacement. In these applications, the file sizes are much smaller than multi-media files, and are frequently updated. For example, a small file may only occupy ¼ of the capacity of the page size, which is quantitatively a small portion of the page and even smaller relative to the memory block associated with the page. However each time the data is modified, which occurs frequently for SSD and cache applications, the entire memory block must be first erased. In FIG. 3 for example, page portions 78 and 80 are both erased prior to a programming operation. As previously mentioned, each memory block includes many pages that store other previously programmed data. Thus well known operations such as page copy operations must be executed to retain the other data that is not being modified. This contributes significantly to reduced endurance of the memory device because the other memory cells in the same page not being modified are subjected to unnecessary erase and program cycles. In the presently described example, the memory cells corresponding to the remaining ¾ of the page are subjected to program and erase cycles. This problem can be addressed with complex wear leveling schemes, but at the cost of degraded system performance. Hence, power consumption is high relative to the small amount of data per page that is to be programmed or modified.